1. Field of the Invention
The present invention relates generally to methods for forming integrated circuit structures within integrated circuits. More particularly, the present invention relates to an electroless plating method for forming copper containing integrated circuit structures within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device dimensions have decreased and integrated circuit device densities have increased, it has become increasingly important to form within advanced integrated circuits conductor structures of diminished dimensions while simultaneously forming conductor structures which exhibit high levels of conductivity and reliability. To assist in forming within advanced integrated circuits conductor structures of diminished dimensions while simultaneously providing conductor structures which exhibit high levels of conductivity and reliability, it is becoming more common within advanced integrated circuits to form conductor structures from copper containing conductor materials rather than the conventional aluminum containing conductor materials, since copper containing conductor materials often provide within various applications within integrated circuits copper containing conductor structures with superior electrical, mechanical and/or thermal properties. See generally, for example, Kim et al., U.S. Pat. No. 5,334,346.
While conductor structures formed within advanced integrated circuits from copper containing conductor materials typically provide within advanced integrated circuits conductor structures having higher levels of conductivity and reliability, conductor structures formed from copper containing conductor materials within advanced integrated circuits are typically not formed entirely without problems. In particular, it is often difficult to form within advanced integrated circuits conductor structures from copper containing conductor materials through conventional photolithographic and reactive ion etching (RIE) methods since copper containing conductor materials are less likely to form volatile species within reactive ion etch (RIE) plasmas employed within those conventional photolithographic and reactive ion etch (RIE) methods.
As an alternative to forming within integrated circuits conductor structures from copper containing conductor materials through conventional photolithographic and reactive ion etch (RIE) methods, it is known in the art of integrated circuit fabrication to employ selective deposition methods such as selective chemical vapor deposition (CVD) methods and selective electroless plating deposition methods to form within advanced integrated circuits conductor structures from conductor materials such as but not limited to copper containing conductor materials. See, for example, Doan et al., U.S. Pat. No. 5,384,284. In addition, with respect specifically to electroless plating deposition of copper containing conductor materials, Goldstein et al. in U.S. Pat. No. 4,265,943 discloses the use of hypophosphite as a reducing agent, in the presence of either nickel or cobalt autocatalysis promoter ions, in order to avoid use of an otherwise conventional electroless copper plating deposition composition which employs formaldehyde as a reducing agent.
With respect to specific copper containing conductor structures which may be formed from plating deposition of copper containing conductor materials within integrated circuits, it is less commonly known in the art of integrated circuit fabrication that copper containing conductor structures may be employed within the core or windings of inductor structures formed within integrated circuits. Although inductor structures have typically not traditionally been employed within integrated circuit fabrications, inductor structures have recently become of interest within integrated circuit fabrications since they may be employed within advanced integrated circuits whose applications are directed towards needs in the areas of matching electrical networks and microelectronic filters.
Methods and materials for forming inductor structures within integrated circuits are generally disclosed by Quirke et al. in "Planar Magnetic Component Technology--A Review," IEEE Trans. On Components, Hybrids and Manufacturing Technology, Vol. 15(5), October 1992, pp. 884-92. Additional examples of specific inductor structures which may be employed within integrated circuit fabrications are disclosed by: (1) Yamaguchi et al. in "Characteristics and Analysis of a Thin Film Inductor With Closed Magnetic Circuit Structure," IEEE Trans. On Magnetics, Vol. 28(5), September 1992, pp. 3015-17 (a trial spiral inductor having a closed magnetic circuit, where the trial spiral inductor is formed with a copper containing inductor conductor core); (2) Ahn et al. in "A Fully Integrated Planar Torroidal Inductor With a Micromachined Nickel-Iron Magnetic Bar," IEEE Trans. On Components, Packaging and Manufacturing Technology, Part A, Vol. 17(3), September 1994, pp. 463-69 (a planar toroidal inductor formed with thick electroplated copper containing inductor conductor windings); and (3) Ashby et al. in "High Q Inductors for Wireless Applications in a Complementary Silicon Bipolar Process," IEEE J. of Solid State Circuits, Vol. 31(1), January 1996, pp. 4-9 (a rectangular spiral inductor formed within a bipolar complementary metal oxide semiconductor (BiCMOS) integrated circuit).
While methods and materials for forming copper containing integrated circuit structures, such as but not limited to copper containing integrated circuit inductor structures, within integrated circuits are thus becoming more common in the art of integrated circuit fabrication, there nonetheless continues to exist concerns within integrated circuits with respect to interdiffusion of copper layers from which are formed copper containing integrated circuit structures with integrated circuit substrate layers upon which are formed those copper containing integrated circuit structures. Such interdiffusion of copper containing integrated circuit structures with silicon oxide and silicon substrate layers typical within integrated circuits has been disclosed by McBrayer et al., in "Diffusion of Metals in Silicon Dioxide," J. Electrochem. Soc., Vol. 133(6), June 1986, pp. 1242-46.
It is thus desirable in the art to provide methods and materials through which there may be formed within integrated circuits copper containing integrated circuit structures with limited interdiffusion of copper containing conductor layers from which are formed those copper containing integrated circuit structures with integrated circuit layers adjoining those copper containing integrated circuit structures. More desirable in the art are methods and materials through which copper containing conductor layers within copper containing integrated circuit inductor structures may be formed with limited interdiffusion of those copper containing conductor layers with integrated circuit layers adjoining those copper containing integrated circuit inductor structures. It is towards the foregoing goals that the present invention is more specifically directed.